Testing of semiconductor devices at the singulated device level, i.e. prior to permanent mounting on an interconnection substrate, is typically conducted with apparatus constructed on the "bed of nails" principle. The devices under test are usually ball grid array or solder bumped ICs with perimeter arrays or area arrays of contacts on one side of the device. The array of contacts is used, after successful test, to flip-chip bond the device to an interconnection substrate.
The test apparatus typically has a large x-y array of contact pins that are brought into contact with the ICs of the device. The pins in the x-y array that align with the pads or bumps on the device are addressed with appropriate electrical circuitry in the test apparatus to apply test voltages to the device contacts and measure the electrical characteristics of the device. Some testers are universal in the sense that pins in the x-y test array will contact any given contact patterns so that different devices with different contact patterns can be tested by modifying the software used to address the array of test pins. Testers can also be made with a permanent custom pin array tailored to a particular chip design. In either case, alignment of the device under test to the array of pins is very critical.
The typical sequence in a manufacture and test facility is to sort the devices as they reach the test facility into a suitable carrier, and convey the carrier to a pick and place tool where the individual devices are placed in a test contactor. The placement performs a critical alignment at this stage between the array of contacts on the device and the contactor. Mechanically the contactor is part of the handling equipment in the manufacturing line, but is also part of the test apparatus. The contactor must handle each device delicately, without damage, and also preserve the critical alignment from the pick and place tool to the test pin array. A separate test contactor must be provided for each device I/O configuration.
In the conventional test procedure the IC device cannot be tested in its final electrical environment. This means that all chip functions cannot be tested, and the IC device is typically not tested at its ultimate speed.